(1) Field of the Invention
The present invention relates to an Large Scale Integration (LSI) packaging technology.
(2) Prior Art
The number of pins in an LSI has been recently on the rise in accordance with a demand for more sophisticated LSIs. On the other hand, a miniaturized package is desired for LSIs in accordance with a demand for miniaturized devices and boards. For this reason, Ball Grid Array (BGA) types shown in FIG. 9A and FIG. 9B and Chip Size Packages (CSPs) have replaced Quad Flat Packages (QFPs) shown in FIG. 8A and FIG. 8B. According to CSP types, the size of an LSI package is substantially the same as that of an LSI chip. According to BGA and CSP LSI packaging technologies, terminals (solder balls) to be connected to the wiring of printed-wiring boards are arranged in a grid pattern on a back surface of an LSI package.
In LSI packages of BGA and CSP, solder balls located near the periphery can be connected, by wires, to the wiring formed on the mounting surface of a printed-wiring board. However, solder balls located in the center part need to be connected to the wiring in an internal layer or a back surface of the printed-wiring board through vias.
A plurality of solder balls on an LSI chip included in an LSI package of the above-mentioned types are disposed as power supply terminals, and at the same electric potential. On an LSI package with such an LSI chip, a plurality of solder balls at the same electric potential are provided as source voltage supply terminals, which are electrically connected to the solder balls on an LSI chip in one-to-one correspondence.
If a switching operation occurs in circuits connected to power supply terminals on an LSI chip in an LSI package, high-frequency currents are generated. To reduce the impact of noise caused by high-frequency currents, it is known to provide an anti-noise unit such as a capacitor element with an LSI package. More specifically, power supply pins and ground pins on an LSI chip are respectively connected to source voltage supply terminals and ground terminals on an LSI package, in such a manner that capacitor elements are disposed between a pin and a terminal. Thus, high-frequency currents are absorbed by capacitor elements. (see Japanese laid-open patent application publication 2001-35952)
If the number of source voltage supply terminals at the same electric potential on an LSI package of the above-mentioned types is reduced, a pitch of terminals as a whole (including signal terminals) on an LSI package can be more or less increased. This makes it easier to connect terminals on an LSI package with wiring.
Here, the number of source voltage supply terminals on the LSI package can be reduced in the following manner. One source voltage supply terminal on an LSI package is electrically connected to a plurality of power supply terminals on an LSI chip. However, when a switching operation occurs in circuits connected to the power supply terminals on the LSI chip, high-frequency currents are generated, and flow into the single source voltage supply terminal on the LSI package. If a switching operation occurs in more than one circuits at a time, a large amount of high-frequency currents are generated. This causes too large a voltage fall in a voltage at the single source voltage supply terminal to be ignored. For example, even though 3.3 V is supplied to an external side of the source voltage supply terminal, only 3.0 V is measured at an internal side of the source voltage supply terminal. Consequently, the power supply terminals on the LSI chip are not supplied with a sufficiently high voltage.
In the light of the above-mentioned problem, it is the object of the present invention to provide an LSI package which maintains the size equal to that of a conventional LSI package, achieves a steady voltage supply with an LSI chip, and have a smaller number of source voltage supply terminals than in the related art.